module FORWARDU(

    input wire is_read_memory_ID_EX,
    input wire is_read_memory_EX_MEM,//jie
    input wire is_write_reg_ID_EX,
    input wire is_write_reg_EX_MEM,
    input wire is_write_reg_MEM_WB,
    input wire [4:0] dest_ID_EX,
    input wire [4:0] dest_EX_MEM,
    input wire [4:0] dest_MEM_WB,
    input wire res_from_csr_ID_EX,

    input wire [4:0] rf_raddr1_ID_EX,// the register number of alu souce 1
    input wire [4:0] rf_raddr2_ID_EX,
    input wire Need_ID_forward1,
    input wire Need_ID_forward2,
    input wire [4:0] rf_raddr1_IF_ID,
    input wire [4:0] rf_raddr2_IF_ID,

    //特权转发
    input wire [13:0] csr_addr_ID,
    input wire [13:0] csr_dest_ID_EX,
    input wire [13:0] csr_dest_EX_MEM,
    input wire is_write_csr_ID_EX,
    input wire is_write_csr_EX_MEM,

    output wire [1:0] csr_src_op,
//id控制
    output wire[1:0] rf_raddr1_src_op_IF_ID,
    output wire[1:0] rf_raddr2_src_op_IF_ID,
//阻塞id之前
    output wire block_flush_ID
);

//特权转发
assign csr_src_op=(csr_addr_ID==csr_dest_ID_EX&&is_write_csr_ID_EX)?2'b10:
                  (csr_addr_ID==csr_dest_EX_MEM&&is_write_csr_EX_MEM)?2'b11:0;






//ld后算术指令阻塞
//id级源操作数未生成阻塞，未实现
//少考虑了在exmem阶段访存且id要用的情况
assign block_flush_ID=(
(dest_ID_EX!=0&&is_write_reg_ID_EX&&(dest_ID_EX==rf_raddr1_IF_ID||dest_ID_EX==rf_raddr2_IF_ID))&& ~res_from_csr_ID_EX ||
(dest_EX_MEM!=0&&is_read_memory_EX_MEM&&(dest_EX_MEM==rf_raddr1_IF_ID||dest_EX_MEM==rf_raddr2_IF_ID))    
);
//id转发
assign rf_raddr1_src_op_IF_ID=(dest_ID_EX == rf_raddr1_IF_ID && is_write_reg_ID_EX && res_from_csr_ID_EX) ? 2'b01:
                        (dest_EX_MEM==rf_raddr1_IF_ID&&is_write_reg_EX_MEM)?2'b10://转发源为ex的执行结果
                        (dest_MEM_WB==rf_raddr1_IF_ID&&is_write_reg_MEM_WB)?2'b11://转发源为mem的执行结果
                        0;
assign rf_raddr2_src_op_IF_ID=(dest_ID_EX == rf_raddr2_IF_ID && is_write_reg_ID_EX && res_from_csr_ID_EX) ? 2'b01:
                        (dest_EX_MEM==rf_raddr2_IF_ID&&is_write_reg_EX_MEM)?2'b10:
                        (dest_MEM_WB==rf_raddr2_IF_ID&&is_write_reg_MEM_WB)?2'b11:
                        0;

endmodule